Analysis of Soft Error Rates by Supply Voltage in 65-nm SOTB and 28-nm UTBB Structures by a PHITS-TCAD Simulation System
نویسندگان
چکیده
We analyze the soft error tolerance of a latch in 65-nm SOTB (Silicon on Thin BOX) and 28-nm UTBB (Ultra Thin Body and BOX) processes by a PHITS-TCAD simulation system. The proposed system is composed of two parts, the device-simulation and the physics simulation by PHITS (Particle and Heavy Ion Transport code System). The alpha and neutron induced soft error rate can be analyzed without test chip and experiment. We investigate the soft error tolerance on 65-nm SOTB and 28-nm UTBB by simulations and experiments. The simulation results are consistent with the experiment results.
منابع مشابه
Analysis of Terrestrial Single Event Upsets by Body Biases in a 28 nm UTBB Process by a PHITS-TCAD Simulation System
We analyze the soft-error tolerance of a latch in a 28-nm UTBB (Ultra Thin Body and BOX) process by a PHITS-TCAD simulation system. It is composed of two parts, a particle transport simulation by PHITS (Particle and Heavy Ion Transport code System) and a device simulation. The neutron induced SERs (soft error rates) can be analyzed by the simulation system. We investigate the soft errors on 28-...
متن کاملAnalysis of the Distance Dependent Multiple Cell Upset Rates on 65-nm Redundant Latches by a PHITS-TCAD Simulation System
Recently, the soft error rates of integrated circuits is increased by process scaling. Soft error decreases the tolerance of VLSIs. Charge sharing and bipolar effect become dominant when a particle hit on latches and flip-flop. soft error makes circuit more sensitive to Multiple Cell Upset (MCU). We analyze the MCU tolerance of redundant latches in 65 nm process by device simulation and particl...
متن کاملEstimation of Soft Error Tolerance according to the Thickness of Buried Oxide and Body Bias 28-nm and 65-nm in FD-SOI Processes by a Monte-Carlo Simulation
1. Abstract We estimate the soft error rates of FD-SOI structures according to the thicknesses of BOX(Buird OXide) layers and body bias on 65-nm and 28-nm processes by reducing the supply voltage. A Monte-Carlo based simulation is used in this work. The parasitic bipolar effect is suppressed by thicker BOX on FD-SOI structure.The simulation results are consistent with the alpha and neutron irra...
متن کاملRadiation-hard Layout Structures on Bulk and SOI Process by Device-level Simulations
This paper analyze the soft error tolerance related to layout structures on 65-nm bulk and SOI processes. The layout structure in which well contacts are placed between redundant latches suppresses MCU effectively. Also the tolerance of SOI structure transistor is estimated by TCAD simulations. The charge collection mechanism is suppressed by the BOX (Buried Oxide) in SOI transistor. Charge sha...
متن کاملSensitivity to Soft Errors of NMOS and PMOS Transistors Evaluated by Latches with Stacking Structures in a 65 nm FDSOI Process
Three different latch structures are fabricated in a 65 nm FDSOI process. We evaluate soft-error tolerance of latches by device simulations and α particle, neutron, heavyion irradiation tests in order to identify which transistor type is dominant to cause soft errors. The latch structure including an inverter with stacked NMOS and unstacked PMOS transistors has enough tolerance against soft err...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2015